Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver

In this paper, a memory efficient Look-up Table (LUT) based address generator for the de-interleaver used in OFDM-WiMAXtransreceiver is proposed. The relationships between various address LUTs implementing different interleaver / de-interleaver depths within a modulation scheme have been exploited to model the proposed address generator. The proposed design shows 81.25% saving of memory blocks in comparison with conventional technique. Hardware structure of the address generator is developed and is converted into a VHDL model using Xilinx Integrated Software Environment (ISE). Simulation results obtained using ModelSim XE-III verifies the functionality of the proposed design. Comparative study of FPGA implementation results of the design on two different platforms is presented. Performance improvement of approximately 30% in terms of maximum operating frequency over a recent work is also obtained.